The present invention relates to memory access control in computer systems, and more particularly to the resolution of conflicts between a plurality of processors in systems with shared memory. It finds particular though not exclusive application in communication systems, and a novel communication system in which the invention may be employed will be outlined briefly.
The basic components of a communications system consist of a set of communication network devices coupled to a device controller which is in turn coupled to a memory. The primary function of the device controller is the scheduling of low-level call and packet handling to and from the network devices. However, a variety of higher-level functions are also required.
A system has been proposed in which two processors are provided, an input-output processor (IOP) and a protocol processor (PP). The IOP performs the scheduling of low-level call and packet handling to and from the network devices, while the PP performs the higher-level functions. The IOP is coupled to the network devices, and the IOP and PP are coupled together and to common memory, which contains the PP code and data, flow tables, data buffers, and data structures shared by the IOP and PP.
In this system, the two processors are both coupled to the same common memory. It is therefore possible that conflicts would arise if the two processors both attempted to access the memory at the same time.
Shared memory systems are known in the prior art, and there have been proposed essentially two systems for resolving conflicts.
One, simpler, system is based on a first come first served principle: if one of the processors is using the memory, it continues to maintain access to the memory until it has finished; if the other processor also wants to access the memory, it has to wait until the first processor has finished. A problem with this system is that the second processor may have to wait for a long period. It has been appreciated that in the context of the communication system outlined above, this may cause adverse consequences if the IOP were unable to service a peripheral device requiring immediate transfer of data to main memory.
In other circumstances, one of the processors may be able to wait for longer periods with no serious ill effects while the other processor may sometimes require relatively prompt servicing (with serious ill effects occurring if it is forced to wait for long periods). This is closer to the situation in the communication system described above; the PP can generally wait without serious ill effects, whereas if the IOP is forced to wait, loss of data may result.
An alternative system has been proposed for such circumstances, based on a priority and interrupt system. In such a system, one processor is assigned a higher priority than the other processor. If the lower priority processor is accessing the memory and the higher priority processor requires access to the memory, the lower priority processor is interrupted while the other processor carries out the memory access it requires.
Such a system could be used in the above described communication system, with the IOP being assigned a higher priority and the PP being assigned a lower priority; this would minimise the risk of data being lost while the IOP waited to access the memory.
The aborting of a memory cycle of the PP will not normally have serious effects on the PP, because the PP""s operations will normally involve waiting when necessary to synchronize its operations with the memory cycles; so the aborting of a memory cycle initiated by the PP will simply result in the PP entering an extended wait state. Normally, if the aborted memory cycle is a read cycle, the PP will have to enter the wait state immediately if action is to be performed on the data just read. However, if the system includes buffering between the PP and the memory, the aborting of a write cycle may not cause the PP to enter the wait state immediately, as it may be able to continue with its processing until the write buffer becomes full.
Nevertheless, the inventor has appreciated that the efficiency of the PP may be seriously compromised in such a system, particularly where frequent accesses by the IOP are performed. In particular, where memory accesses involving a read or write of a burst of data are involved, the PP may have its cycles aborted frequently, and there is usually significant overhead associated with the beginning of a memory cycle, which will be lost every time the cycle is aborted. Thus, the PP may spend a significant proportion of its time beginning memory accesses which are subsequently aborted.
For the above reasons, it would appear on the face of it desirable to reduce the use of shared memory by the processors. However, the inventor has appreciated that advantages would accrue if the problems of shared memory access could be alleviated; for example, the two processors may be fabricated on a single substrate, employing common external memory, and data transfer may be facilitated by use of the shared memory.
Thus the general aim of the present invention is to provide a memory management system which alleviates or overcomes the above problems or disadvantages.
U.S. Pat. No. 4,400,771 describes a multiple processor system with a common memory, where priority of access to a shared memory system is under programmatic control through a register, i.e. variable but static on a cycle by cycle basis as predetermined through a register. U.S. Pat. No. 3,798,591 describes a system for multiple processors to access multiple storage devices on a fixed priority scheme. Storage units, which are in use by a particular processor, respond with signals to prevent access from other processors. U.S. Pat. No. 4,829,467 describes a resource sharing system but deals in detail with how a DRAM, in a memory system, arbitrates between normal accesses and higher priority accesses on a dynamic basis. The dynamic basis used is the number of previous accesses. U.S. Pat. No. 4,493,036 describes a dual port memory system with a dynamic priority allocation system. The latter works by breaking priority resolution into two stages: initial and final. A two stage priority resolution process allows an initial request to be regraded as a high priority request at a later stage within the same priority resolution cycle.
At least in its preferred embodiments, the invention enables at least two processors to have equal access but if one processor wished to access memory with a higher priority than the other, then the first processor""s access would be interrupted. Priority access is also based on traffic conditions namely, the state of one or more peripheral devices attached to the respective processor.
Features of the invention are defined by the attached claims.
In the present invention, as long as the processors are all operating at the same priority level, whichever processor happens to be accessing the memory will be able to complete its access, with any other processor having to wait its turn. But if the second processor is accessing the memory and the first processor calls for a memory access with higher priority, then the second processor can be interrupted and the first processor can obtain immediate access to the memory. The loss of clock cycles resulting from such interruption therefore occurs only when the first processor cannot wait and interruption is essential.
Other preferred features and other aspects of the invention are set out in the claims.
It will of course be realized that, although possible, it is not essential for the system to be symmetrical (for each processor to be able to access the memory with each level of priority). In the communication system described above, for example, if the buffer of a device receiving incoming data is approaching overflow, it is important for the IOP to attend to that device urgently. The IOP therefore needs to be able to interrupt the PP. The PP""s operations, however, are generally not time-critical, so the PP does not need to be able to interrupt the IOP. In other words, the IOP must be able to produce priority level signals at both high and low priority levels, while the PP only has to be able to produce a priority level signal at the low level.
Although preferably employed in a two-processor system, for example as described above, the system may be extended to more than two processors, in which case some means will normally also be required to resolve conflicts between processors at the same priority level. Various options are available for this, such as a first come first served basis (using a queue), a fixed priority sequence, or a round robin system.
It should be noted that the function of the memory access controller may be integrated with one or more of the processors; indeed, in the preferred application where the controller and processors are integrated on a single substrate, there may be no clearly defined physical boundary between the functional components. Additionally, the memory access controller may be integrated with components which detect the second state for other purposes; for example, where the second state corresponds to an imminent demand for service by one or more peripherals, for example based on buffer occupancy, a portion of the memory access controller may be integrated with components for determining a servicing schedule for the peripherals.